System on Chip (SoC) designs being developed today have millions and millions of gates. The complexity of the designs combined with the devices using the SoC designs in industrial products has made design verification an essential element in the semiconductor development cycle. Thus, prior to manufacture, the hardware designers frequently employ emulators to verify the functional behavior of the electronic devices and systems fabricated in accordance with their designs. One type of verification system for a hardware device under test (DUT) is a hardware emulation system that generally provides an effective way to increase verification productivity, speed up time-to-market, and deliver greater confidence in the final SoC product. It provides a processor-based emulation system, which is in communication with a workstation that sends data to and from the DUT. Such data can include digital test vectors or real signals from a logic system for which the DUT is intended.
Conventional hardware emulation system include coupling systems for coupling the hardware emulation system with a target system. The target system is the operating environment where the DUT, once manufactured, will be installed. The hardware emulation system is configured to couple with the target system via communication cable assemblies. The communication cable assemblies form a target interface system for coupling the hardware emulation system and the target system. The communication cable assemblies may include an emulator connector assembly and a target connector assembly that are coupled via a communication cable. The target connector assembly is a piece of hardware that is located away from the hardware emulation system and connected to the target system. The target connector assembly may include a connector assembly and a pod. The pod is an interface system of the target system.
Most of the devices in the hardware emulation system communicate to each other through a PCI bus because all the devices are located inside a rack of the hardware emulation system. However, the pod is not located in the rack of the hardware emulation system, and there is no PCI interface linked to the pod so the communication between the hardware emulation system and the pod occurs using other interfaces. The communication by the hardware emulation system to the pod may be performed through an Ethernet port. The Ethernet port communicates with a low powered processor inside the pod called a board manager. Also, the communication by the hardware emulation system to a field processor gate array (FPGA) in the pod to transfer runtime data may occur through a low-speed interface such as UART. The UART works sufficiently for transfer of regular run time data, but is insufficient for sending large amounts of data to the pod. When the pod has to be reprogrammed, a large amount of data has to be sent from the hardware emulation system to the pod. The data sent through the UART takes a significant amount of time to transfer.
Therefore, there is a need for methods and systems that addresses the above mentioned drawbacks of the conventional techniques employed for data transfer between the hardware emulation system and the target system, and is thereby able to achieve optimal performance for compiling time as well as runtime when a large amount of data has to be transferred between the hardware emulation system and the target system.